Now that you are telling that, I remember that was one reason I did not explore that path.
Another reason is that the 6-bit volume change is not synchronous with the 8-bit sample change.
Potentially, you can get quite some 15-bit sample changes over a 256-cycle window.
Ah yes. (Fun fact: the Amiga's volume control was apparently implemented as a PWM gate on the audio path.) I would imagine registering the volume transitions to become synchronous with the sample edges would be possible, though, and wouldn't impair accuracy to any great degree.
On the other hand, putting only the new DAC is quite trivial but you will get that metallic sound.
Indeed - I've got the DAC itself working on the cheap EBay CIII board I've been using for experimentation.
The output of the 3rd order filter seems rather attenuated compared with the simple 1st order filter I've been playing with, though. Is this a side-effect of the algorithm, or a deliberate choice to keep the output at line level when driven from 3.3v?
You can try also a simpler 1st order IIR filter. The article from Antti Lankila gives some good hints : http://www.bel.fi/~alankila/modguide/interpolate.txt
Ah thanks for that - I've just had a quick peep, and there's some good info there.
Edit: by the way, is there a practical upper limit to the frequency at which a sigma delta DAC can run before imperfect waveforms on the output pins of the FPGA become an issue, or is it OK in practice to run them at near the fmax?