Hoy folks !
As a personal learning exercise, I've been using Minimig to implement a Mac+ core. It's still a work in progress, it boots to Finder from an emulated SCSI disk, but there's no mouse or keyboard yet
I'll post everything somewhere, maybe along with some kind of blog post explaining what I did, when I'm a little further along, however, being a reasonably n00b when it comes to HW design (I'm a SW person), there are a few things that I haven't managed to get my head around so far.
The main one is timing, as I suppose is to be expected. I don't totally get the meaning of the constraints in the Minimig UCF (and last I tried, recent Xiling ICE didn't like them either). I'm having timing closure errors from Xilinx tools on my video clock and my main 16Mhz clock, mostly on components that cross the clock domains (typically on the first gate of synchronizers), and I'm not sure whether that's just normal or if something needs to be done.
Also, it looks like the crystal used on Minimig (4.7Mhz) is outside of the DCM "happy" ranges. You can't run a DLL with less than 18Mhz on the input source, and in fact, if I use the DCM as a simple FX synthetizer, it also complains that 16Mhz is too slow (too long a period) for it to generate. When I tried to stack a DCM synthetizing a 33Mhz that I then fed into a DCM as a DLL, it spat out various warnings as well (I don't have them right at hand, but I can dig if it's of interest).
But then 33Mhz isn't what I want for a DLL.
What I really want is a 16Mhz all accross my entire design (yeah, my Mac is a bit overclocked
except video. I use that same clock to generate the CPU clk (using a trick recommended by Xiling, feeding an OFDDRCPE with clk & ~clk). For video I generate something close to a 25Mhz using another DCM in pure FX mode. My pixel pipe is clocked off that and I have some async signaling to the my memory controller to get the pixels (with synchronizers to cross the clock domains).
Any tips/recommendations welcome.
Login
Register
FAQ
Search
