Minimig Discussion Forum

Isn´t it possible to multiplex the address and data lines in order to save some IO pins somehow ? Even though, one must do voltage conversion, it must be possible to connect it somehow. Even if it means to add it as a daughterboard with some extra logic on that board to server as a gateway to the minimig.

Espen

Minimig V1.1 board has 3 spare IO lines for free use. Even if the single 15/31KHz jumper line is used as data/address line it would make only 4 wires to connect a chip with at least 8 data in/out lines and 5 address lines. Additional control lines (clocks, we/ce, reset etc.) would be required.
To do this only on 4 lines it would require a huge amount of multiplexing, buffering logic and fpga coding. Also as already mentioned an external daughterboard to host the SID and additional logic. All this only to have "real" C64 sound output? As Dirk said another fpga developer board would take this more easy. Minimig is not designed to be a developer board. Its nice to see other kind of core working on it

Right now Im busy in learning Verilog and VHDL to be more sure of what Im doing and also able to adapt/port some thing to this fpga and pcb. Until now I had some positive resolts in building (very simple) own core files for it.
Currently Im porting this free "Pong" clone: http://www.fpga4fun.com/PongGame.html

Cool. I will check it out. BTW: Can you let me in on which tools I need to download and what pre reqisities needed to start loading sources, compiling them and get the .bin file out to load onto the sd card to test on the minimig ?

I just downloaded the webpack from xilinx plus the foundation 10.1 but I am not sure if these are the right ones. You seem to have managed to get over the edge and start making use of the knowledge aquired in order to port cores.

Would you mind taking 5 mins and throw some info out..just to enlighten the others who also find fpga programming interesting, but are not yet gotten to the point where you are now ?

1. Which SW to download, and from where
2. Names of tools needed, and what they do
3. A test source to try out
4. How to compiled and apply it to the sd card in order to test it


If you had time to do this, I would be insanely happy (does that make sense ? hehe)


Espen

Yep Xilinx ISE Webpack is the right thing to compile FPGA core for Minimig Spartan3.

Im also using version 9.2i because 10.1 don't want to compile the current minimig sources from Jakub. If you want to create own new projects (for testing something) 10.1 will do fine!
Version 9.2i can still be downloaded on Xilinx website, you have to select the previous version by hand.

I will try to make a short (hopefuly understandable) depiction how to start a new project till compiling into .bin file.
You will have to download the current minimig source file (http://home.hetnet.nl/~weeren001/downloads/minimigJ_source_04_08_2008.zip) and unpack it somewhere. Then:

Start ISE Webpack frontend... sure, what else I dont know the windows start menu name. As you will see Im using Linux here.


To start a new project select "file" > "new project" in pull-down menu. You will see this:

Type in the name of your project, in this case "Minimig1". ISE will name the path to all project file the same... but you can also alter it. Let everything else at default and select "next".



Now you have to set the right hardware specs to your FPGA. For the Minimig board you will need this settings:

Select Next to go on...



The following window can be skiped unless you only have one source file to add.
Minimig is based on several source file, so just go "Next".

In next window we can add all the source file at once:

Select Add to see file import window:



Choose your source path (just expanded out of .zip file) and press CTRL+A to select all files.

Select Open to add this sources to the new project.



All source (.v) files will be listed as here:

Select Next to continue...

Next window will show a summary of the new project... its just an info so I will not post this picture here.
Select Finish to continue.

In following window all sources will be included, it take only a few secs and all .v file symbol should have a green check.

Select Ok when everything is right (green ) to finish this step.



Now you should see the main window of ISE:

I will base upon this window because its too much upload for only little changes.

On the upper left you will find all the project sources and sub-sources (+). First we let them right there and take care of some necessary settings.

Select projects "top module" in the upper left part - as visual in the picture above.
Click "Create Programming File" with right mouse bottom in the lower left part. Then select "Properties..."


The following window will show up and you have to check-on this black bordered function for .bin file creation.:

Select OK to ack.



Now all basic settings are done and you can start of compiling the sources into .bin file. It will be named as the project is, so you will find some Minimig1.bin in the sources path. There are also many other "Minimig1.xxx" files too, dont worry about them right now.
If you start any other new project, the resulting "MyProject.bin" file always has to be named "Minimig1.bin" to be used on sd-card for Minimig bootup sequence. The PIC chip will only search for this file name!


To start compiling process you have to right click "Generate Programming File" again and select "Return" or "Return All".
If available you can also choose "Run" but this is a special recompiling case and will be unavailable right now.

Now this lightblue "route forms" should rotate. Sometimes they all do and sometimes only one after another (ISE is a complex thing ).
Once its finished, depending on your computers speed, you will have your own compiled Minimig core on harddrive!

PS: ignore all warnings during compiling time. Also ignore a yellow "!" sign on the left side of "Create Programming File". Only Error's are importand, compiling process will stop right there and point out some error message.
But everything else will do just fine.

I hope it was understandable and will work for your benefit.
If I missed something or any kind of error/problem will occur, feel free to ask about it.
At first I also needed help to handle this software and it took me 1-2 days to find out how to get this .bin file out.

Good luck and yes happiness does make sense
B4k

Truly awesome, dude. Thanks for this incredibly good tutorial on how to compile it. I have now uninstalled 10.1 and reinstalling 9.2i at the moment to be sure I get it all right. Compiling the minimig source is a great way to see how things shall work. After that I can try to adapt the pong game from fpga4fun so it works with minimig and its vga+ps2 ports. It probably is a lot of work to get it to work as i have no idea on how to do it, but since i am totally blank, any progress is good progress

BTW: I am very insecure whether I want to start doing vhdl or verilog. Verilog looks much more intuitive as a language, but as i understand, vhdl is probably better to learn (industry-wise). What is your experience and opinion on this ?


Regs
Espen

To compile with ISE 10.x add following statement to spiclk net in constraints file: CLOCK_DEDICATED_ROUTE = FALSE

Oh, I just deinstalled 10.1 and reinstalled 9.2i with SP4 Now I regret that hehe...
Still, i Guess 9.2 will give me as much fun as I need anyway

Boing: It worked nicely. Everything compiled as it should. Now I can start to see if I can make some testprograms for the minimig and maybe try porting that damn Pong game )))

Espen

@palm
You are welcome. ISE Webpack 9.2i is working fine, V 10.1 is not really necessary "to us" afaik. Even Dennis v. W. developed the first 2 Minimig core using ISE 6.x as he told me in some email.

@all
Can somebody please give me a little advice in building own dcm? It seems Im unable to do so... Also some changes dont show any effect to the recompiled core. If this will work, Pong and some other portings will also work very fine on Minimig!
Thx