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//----------------------------------------------------------------------------------
//----------------------------------------------------------------------------------
//interrupt control
//----------------------------------------------------------------------------------
//----------------------------------------------------------------------------------

module ciaint
(
   input    clk,              //clock
   input   rd,               //read enable
   input   wr,               //write enable
   input    reset,             //reset
   input    icrs,            //interrupt control register select
   input   ta,               //ta (set TA bit in ICR register)
   input   tb,                //tb (set TB bit in ICR register)
   input   alrm,             //alrm (set ALRM bit ICR register)
   input    flag,             //flag (set FLG bit in ICR register)
   input    ser,            //ser (set SP bit in ICR register)
   input    [7:0] data_in,      //bus data in
   output    [7:0] data_out,      //bus data out
   output   irq               //intterupt out
);

reg  [4:0] icr;         //interrupt register
reg  [4:0] icrmask;      //interrupt mask register
wire       icr_rd;      //interrupt control register read
reg        icr_rd_dly;  //interrupt control register read delayed

//interrupt control register read
assign icr_rd = icrs & rd;

//interrupt control register read delayed
always @(posedge clk)
   if (reset)
      icr_rd_dly <= 0;
   else
       icr_rd_dly <= icr_rd;

//reading of interrupt data register
assign data_out[7:0] = icr_rd ? {irq,2'b00,icr[4:0]} : 8'b0000_0000;

//writing of interrupt mask register
always @(posedge clk)
   if (reset)
      icrmask[4:0] <= 0;
   else if (icrs && wr)
   begin
      if (data_in[7])
         icrmask[4:0] <= icrmask[4:0] | data_in[4:0];
      else
         icrmask[4:0] <= icrmask[4:0] & (~data_in[4:0]);
   end

//register new interrupts and/or changes by user reads
always @(posedge clk)
   if (reset)//synchronous reset   
      icr[4:0] <= 5'b0_0000;
   else if (!icr_rd && icr_rd_dly)
   begin//clear latched interrupts on end of read
      icr[0] <= ta;         //timer a
      icr[1] <= tb;         //timer b
      icr[2] <= alrm;         //timer tod
      icr[3] <= ser;          //external ser input
      icr[4] <= flag;         //external flag input
   end
   else
   begin//keep latched interrupts
      icr[0] <= icr[0] | ta;      //timer a
      icr[1] <= icr[1] | tb;      //timer b
      icr[2] <= icr[2] | alrm;   //timer tod
      icr[3] <= icr[3] | ser;      //external ser input
      icr[4] <= icr[4] | flag;   //external flag input
   end

//generate irq output (interrupt request)
assign irq    = (icrmask[0] & icr[0])
         | (icrmask[1] & icr[1])
         | (icrmask[2] & icr[2])
         | (icrmask[3] & icr[3])
         | (icrmask[4] & icr[4]);

endmodule