Is the SPI communication protocol between FPGA and PIC described somewere?
There is no separate detailed description but some info is available in the sources.
I have done a porting on a Cyclone III board with no external ARM or PIC.
I first tried to keep the floppy.v file with the SPI slave controller connected to a NIOS II CPU with a SPI master controller but the SPI was getting out of sync.
Finally, I rewrote the floppy controller with a parallel interface to the FIFO and to some control registers. The NIOS II CPU can "see" the DSKLEN and DSKSYNC registers of the Minimig and the pseudo MFM encoding and byte swapping is done by the HW.
As a consequence, the source code in FDD.c and FPGA.c is a lot shorter and simpler.
The execution speed is also much faster and I just need 2KB of FIFO space instead of 4KB (I just have 10 MIPS on the NIOS II).
You should consider this option.