If you're going to be fixing this stuff, can you do it in a general enough way that the fixes can be ported over to the Chameleon core?
I'm trying to be as board- and FPGA- agnostic as I can be, but certain things are very specific to a particular implementation. For example, the original Minimig hardly needs any timing constraints, and it will work just fine. The DE1 implementation is another issue, specifically because of the use of SDRAM memory, and very high clock frequencies - both TG68 cores and the SDRAM controller run at over 100MHz. I still need to check why exactly does the TG68 core need such high frequencies.
Excellent The changes I made to the TC64's ARM replacement firmware are available here, if they're of any interest?
Yes, thank you. I'll work on that next.
IIRC, the design has two TG68 cores, it might be good to replace the core used for the OSD by a NIOS II/s, the CPU takes only 700 LEs and is more powerful than a TG68. If you do not like the NIOS II option, another good candidate is the AVR core.
Yes, the AVR core might be a good candidate. The NIOS is unfortunately not open-source and requires a license for use. Another possible soft-core CPU is the Lattice Mico.
Otherwise I'm almost done rewriting VHDL code to Verilog, I just need to finish the TG68 core and the SDRAM controller, which are mostly done, but untested. This will, among other things, allow me to run some high-speed simulations using Verilator.
There's a new build
available, which contains many under-the-hood changes, I also (re)implemented keyboard joystick emulation, which works with current rtl/fw sources.
Please test it, and report any compatibility issues you find. Especially watch for anything that used to work and doesn't anymore