Minimig Discussion Forum

That is really good news! I need to check that out at once

Unfortunately, the bad news is, there is currently no way to fit the new TG68.K core inside the DE1 - it's twice the size of the current core.

It looks though that the new core supports multiple configurations, maybe if just one is selected, the size would come down.

Can you PM me your e-mail address, I can send to you my core.
It is really small (~1900 LEs) but needs 14 M4k on a Cyclone II.

Another good candidate for optimization is the Agnus chipset.
The real chip has only one address ALU whereas the Minimig one has 6 of them.
Moreover, the Cyclone FPGAs are not very efficient with distributed RAM.
It is possible to use the AR3 custom register shadow RAM block to also store the PTR, LOC and MOD registers (~1000 LEs saving).

Regards,

Frederic

frenchshark:

Yes, please send me your core and I'll have a look at it.

I'll take a look at Agnus implementation if any possible optimizations can be done. Yes, the Altera FPGAs dont's support distributed memory, only block memory or register memory. AFAIK only Xilinx supports dist. memory. Altera does support splitting of block memory in some cases, though.

Otherwise, I did manage to fit the whole project from Tobias inside the FPGA on the DE1 board. There were only about 100 LEs left, and no pins were assigned, so there's no way that would ever actually work.

I won't bother with the new TG68 core at the moment. I think there's more important work to be done, especially regarding various timings. There are some huge FPGA no-nos inside the current implementation - using clock as data, using inverted and non-inverted clock in the same logic, using logic generated clocks, no constraints on i/o pins, I think I saw even some clock gating somewhere. It is best to avoid such code, because it makes timing analysis almost impossible.

So that's what I'm working on at the moment, I'm also trying to minimize the design wherever I can - I did already manage to free some 20k memory bits. Next, I'll work on the changes in Userio.v and PS2Keyboard.v, together with updated "ARM replacement" firmware.

Enjoy!

If you're going to be fixing this stuff, can you do it in a general enough way that the fixes can be ported over to the Chameleon core?



Excellent The changes I made to the TC64's ARM replacement firmware are available here, if they're of any interest?
https://github.com/robinsonb5/minimig_tc64
(My changes amount to slowing down scrolling of overlong filenames to a sensible speed and adding block-level SD-card access - with a maxtransfer fix to the latter from Tobiflex.)

Last time I looked at the DE1 Minimig source, I have noticed the same issues.
IIRC, the design has two TG68 cores, it might be good to replace the core used for the OSD by a NIOS II/s, the CPU takes only 700 LEs and is more powerful than a TG68. If you do not like the NIOS II option, another good candidate is the AVR core.

Regards,

Frederic

I'm trying to be as board- and FPGA- agnostic as I can be, but certain things are very specific to a particular implementation. For example, the original Minimig hardly needs any timing constraints, and it will work just fine. The DE1 implementation is another issue, specifically because of the use of SDRAM memory, and very high clock frequencies - both TG68 cores and the SDRAM controller run at over 100MHz. I still need to check why exactly does the TG68 core need such high frequencies.


Yes, thank you. I'll work on that next.


Yes, the AVR core might be a good candidate. The NIOS is unfortunately not open-source and requires a license for use. Another possible soft-core CPU is the Lattice Mico.

Otherwise I'm almost done rewriting VHDL code to Verilog, I just need to finish the TG68 core and the SDRAM controller, which are mostly done, but untested. This will, among other things, allow me to run some high-speed simulations using Verilator.

There's a new build available, which contains many under-the-hood changes, I also (re)implemented keyboard joystick emulation, which works with current rtl/fw sources.

Please test it, and report any compatibility issues you find. Especially watch for anything that used to work and doesn't anymore

Enjoy!

I might be being stupid here, but I can't get the joystick emulation to work - which keys are mapped to what? (Also any support for mouse buttons? I haven't rigged up a PS/2 splitter yet, so I'm running keyboard only on my newly-acquired DE1.)

The joystick emulation uses the cursor movement keys (up, down, left right) and the LeftCTRL for Fire1 and LeftALT fot Fire2. The mouse buttons emulation is currently not enabled - I'll fix that, I just have to insert some AND gates somewhere

The PS/2 splitter will not work unless you solder some wires & resistors from the GPIO pins to the PS/2 connector.

Enjoy!

Hmmmm OK. And do I have to turn it on and off with NumLock or anything like that?



Ah, OK - in which case it'd be as easy to just wire up a second PS/2 port to the GPIO header, wouldn't it?